This invention relates to a data processing system, and more particularly an improvement of a branch instruction prefetching processing executed where a judging step is included in the steps of processing an instruction sequence.
Suppose now that a group of instructions including one or more branch instructions forms an instruction sequence stored in a memory device. When executing such an instruction sequence, prior to the execution of a branch instruction, an instruction stored in an address of the memory device designated by an address to which the branching is to be made, and an instruction following the branch instruction are prefetched and after executing the branch instruction, an instruction to be executed next to an instruction which became evident as a result of executing the branch instruction is used to actuate a processor. Such a system is disclosed in U.S. Pat. No. 4,200,927, dated Apr. 29, 1980. This system is constructed such that even when two branch instructions serially included in the instruction sequence are executed, the prefetching of these two instructions is possible. More particularly where a branch instruction which transfers control in one of two directions appears twice during the prefetching operation, for the purpose of executing instruction sequences in three directions, that is an instruction sequence already executed, an instruction sequence of the two branch sequences which were branched in the success side according to the first branch instruction, and an instruction sequence branched in the success side in accordance with the second branching operation, the system is constructed such that the instructions in the three sequences can be prefetched and stored in three independent instruction buffers. With this construction, however, since prefetchings are performed in three directions, as the number of times of accessing to the memory device increases, the processing speed of the system decreases. Also as shown in U.S. Pat. No. 3,723,976, a system has been proposed to use a cache memory device for the purpose of increasing the processing speed of the system so as to prefetch from a main memory device instructions in three directions for storing the prefetched instructions. This system, however, also is required to store in the cache memory device also information not used in the main memory device during the excuting operation so that information that is used frequently would be replaced from the cache memory device to the main memory device. Consequently, the percentage of storing in the cache memory device data desired by a central processing unit (CPU) decreases, thus failing to decrease the processing speed of the system.